The PCB layout is of primary importance in determining the QPLL performance. Because of that, a section was introduced in the QPLL manual where a specific layout is recommended for the interconnections between the ASIC and the quartz crystal. The QPLL users must guaranty that these recommendations are followed in their PCBs. Failing to do so will result in either a reduced locking range or in total impossibility to lock to the LHC clock frequency. It is thus strongly recommended that the users read the section on the manual concerning layout.

The schematic and PCB layout of the TTCrq can be taken as an example of how the QPLL and the crystal should interconnected.