A test fixture was developed for evaluation and production testing of the QPLL. The fixture schematic and layout information is available through CERN's EDMS service.

The QPLL test fixture was developed to allow automatic testing and characterization of the ASIC. Two instantiations of the IC are found in the schematic and layout: in one case the ASIC is mounted on a test socket while in the other it is directly soldered to the PCB. The test socket will be used for production testing while the soldered ASIC will allow to characterize the QPLL center frequency with a specific PCB layout. Using the two mounting options will allow to determine the frequency shift resulting from the additional circuit parasitics introduced by the test socket and thus to have their effects into account during the production tests.

To facilitate the CAD work a schematic capture symbol and the layout footprint of the ASIC (LPCC) are available in the CERN CADENCE library. The footprint is available in the library CNSPECIAL under the name QPLL. The package type LPCC option must be used.

The schematic and layout are given here for information purposes only, the circuit will not be available to the QPLL users and, consequently, no user support will be given.